1. Field of the Invention
The present invention relates to the field of buses and bus bridges, and more particularly to a method and apparatus for optimizing the management of buffers within a bus bridge.
2. Art Background
Many computer systems incorporate at least two buses. A first bus, commonly referred to as a memory bus, is typically used for communications between a central processor and a main memory. A second bus, known as a peripheral bus, is used for communications between peripheral devices such as graphics systems, disk drives, or local area networks. To allow data transfers between these two buses, a bus bridge is utilized to "bridge" and thereby couple, the two buses together.
The primary task of a bridge is to allow data to cross from one bus to the other bus without diminishing the performance of either bus. To perform this function, the bridge must understand and participate in the bus protocol of each of the buses. In particular, the bridge must be able to serve in both a slave capacity and a master capacity such that it can accept a request from a first bus as a slave, then initiate an appropriate bus operation on the other bus as a master. The bridge must, therefore, provide support for accesses crossing from one bus to the other bus.
Typically, a bridge utilizes data buffering such that data to be transferred through the bridge from either the memory bus or the peripheral bus is temporarily stored, or "posted," within a data buffer. Posting data in a bridge can enhance the performance of the system by packetizing data and pre-fetching data, but can also introduce a problem of data consistency when synchronization events occur. These synchronization events can include interrupts, processor accesses of status registers within agents, or processor accesses of a predetermined address in shared memory space serving as a flag. When a synchronization event occurs, and data remains posted in the bridge, data inconsistency can result.
Certain systems address the issue of data consistency by forcing the bridge to participate in the cache protocol of the memory bus. This solution, however, forces a high level of the complexity onto the bridge and tends to be expensive. As will be described, the present invention addresses the issue of data consistency through a less complex and costly method and apparatus. In particular, the present invention intercepts synchronization events and selectively flushes data buffers within the bridge.